A silicon die with high density inputs/outputs (I/O) typically requires an organic substrate to facilitate integration on a system board. A substrate usually consists of a core at the center and multiple layers of metal interconnect on both sides of the core. A dielectric insulating layer is usually placed between adjacent metal layers to electrically isolate the metal layers from one another. A substrate facilitates formation of an electrical link to the system board. It protects the die and modularizes the product development effort while simplifying the subsequent integration steps involved in the manufacturing of a larger computer or a consumer electronic product. The present trend in substrate technology is to transition from ceramic-based chip carriers (substrates) to organic material-based chip carriers. An organic polymer-based electronic chip carrier (substrate) is a cost-effective means to fan out I/Os and power connections from a high density silicon integrated circuit chip (semiconductor die).
The core of organic chip carriers (substrates) is typically about 400-800 μm thick and made of a fiber-reinforced organic or resin insulator material. In order to reduce cost, the core is eliminated in some substrates (e.g., coreless substrates). The metal interconnects are progressively built layer-by-layer on top and bottom surfaces of the core by a series of process steps. Most metal layers are patterned, while some metal layers are solid (e.g., metal ground or power planes). The steps involve electroless-plating, electroplating, etching, polishing, placement of dielectric resin, high temperature pressing of resin to form a laminate. Each circuit layer or a power or ground plane is separated by a sheet of photosensitive resin. Laser drilling of the resin followed by an electroplating process are used to fabricate vias (sometimes referred to as plated through holes PTH) that help connect the various metal layers. Multi-stack vias are used to link layers that are further apart within the build layers of a substrate.
The buildup layers between the die and the core are often referred to as “FC” (front circuit) layers, and the layers on the opposite side of the core are often referred to as “BC” (bottom circuit) layers. Since each metal layer is typically designed to optimize electrical performance, the mechanical characteristics of each layer are not precisely controlled. The FC layers generally have dense interconnect structure made of a pattern of metal lines, typically etched from a layer of copper deposited by means of a plating process. The BC layers, on the other hand, tend to be formed as a continuous sheet of copper with distributed holes for vias to pass through. Such a configuration inevitably leads to a substrate with asymmetric thermomechanical properties when viewed with respect to the center plane of the core.
A substrate design with asymmetric thermomechanical parameters can exhibit significant warp when it is constructed at high temperature and then cooled down to room temperature. Electronic manufacturing and assembly operations incorporating a substrate generally require a minimum acceptable warp. For example, for a substrate with 55×55 millimeter (mm) dimension in x-y, a warp up to 100 micrometers (μm) is usually considered acceptable. As the number of buildup layers and core thicknesses are changed, the warp levels can change according to their interaction with one another. The yield of substrates can be undesirably impacted if parametric symmetry is not maintained within corresponding limits.